According to the Taiwanese edition of the Commercial Times, TSMC is positive about the development of the 2-nanometer process. Moreover, the company denied rumors about the delay in the appearance of such processors. At the same time, competitors are also not sitting idle.
Earlier, rumors appeared on the network that TSMC intends to postpone the start of mass production of 2nm processors to 2026 due to technical problems. However, TSMC’s vice president of process engineering, Zhang Xiaogang, recently told reporters that the development of the 2nm process is going smoothly, and mass production should be established in 2025 as planned.
In addition, TSMC CEO Wei Zhejia said that they expect demand for 2nm process technology to exceed demand for 3nm and 5nm processes. However, he added that the company intends to triple its 3nm production capacity by the end of this year, but even then, they won’t be able to handle all orders.
TSMC’s ambitious roadmap for its 2nm manufacturing process has sparked significant attention. The chipmaker is set to begin the mass production of its 2nm process node in 2025.
Amid the furor and speculation, it remains unclear when 2nm can realistically start rolling off production lines. With much talk of geopolitics, location, and timescales, just how grounded is TSMC’s claim that it’s going to turn on the assembly line of 2nm wafers next year?
According to the roadmap and on TSMC’s 2nm logic section of its website, this next level and brand-new node plans to bring some key technologies to the fold. We’re talking about the gate-all-around (GAA) transistor architecture and backside power delivery networks. The payoff of these? Well, they allegedly offer better performance and greater power efficiency than architecture on its N3 node.
The addition of the GAA transistor technology marks a departure from the FinFET designs that have dominated process nodes all the way back since 22nm. While GAA offers better electrostatic control and power efficiency, it’s not without its challenges. Manufacturing nanosheet or nanowire structures at scale is like threading a needle blindfolded; it’s a highly complex process and as an advanced node, it brings the added pressure of keeping defects to an absolute minimum.
That’s not the end of it though, as TSMC plans to pair GAA with backside power delivery, which is a fancy way of saying the power lines will be routed below the transistor, not above. It’s a clever and intricate design that frees up space for the signals on top, but implementing it is no small feat. So, what’s the reality of it all? Well, combining these two innovations should make things more complex for TSMC’s engineers and fabs. For reference, TSMC actually decided not to include BSPD in its N2P node on 2nm, but it is set to make an appearance through its A16 node, also referred to as 1.6nm.
Dodging high-NA headaches
So, let’s talk about the lithography, because no conversation about 2nm is complete without mentioning the extreme ultraviolet (EUV) tools that are critical to manufacturing. TSMC has stated its initial 2nm runs won’t rely on high-NA EUV (the next-gen version of EUV lithography), which is lucky really, because the expensive machines, which cost around $370 million each, actually don’t exist yet in any meaningful quantity.
In fact, while ASML typically does not comment about its customers and the orders, the only High-NA EUV machines that seem to have been shipped and confirmed so far have both been received by Intel; TSMC is reportedly expecting delivery of one by the end of 2024. ASML, the Dutch firm and global leader in lithography tools, is responsible for these, and it is years away from ramping up production to meet demand. As it stands, it is estimated to be able to produce between five and six High-NA EUV units per year, so there could be a couple more machines out there.
By skipping high-NA EUV for the initial production run, TSMC avoids one immediate headache, but this also means the early 2nm process could lack the full performance and efficiency improvements as touted in its roadmap. If indeed TSMC does as it says and gets 2nm in full production in 2025, it might keep the headline intact, but the underlying story does look a little shakier.
Taiwan digs in: Core tech stays home
So aside from the above, there’s also the political side and the obstacles that government regulation typically brings. Taiwan via their Minister of Economic Affairs, JW Kuo, made it abundantly clear that TSMC’s most advanced nodes will stay on home soil for the foreseeable future. This is where things get a little cloudy from the “you can’t have it because it belongs to us” prattle. As part of TSMC’s Fab 21, which is currently being built in Arizona, US, two of the three fabs that are to be built according to TSMC will manufacture using the 2nm node.
The Taiwanese government might stamp its feet and state that it has no intention of letting its chipmaking crown jewels leave the island, at least until a newer process supersedes it. If taken literally, it may stall TSMC’s Arizona fabs from rolling out 2nm until 2027 or around then.
However, TSMC’s second fab at Fab 21 in Arizona, planned to bring 2nm production to US soil, isn’t expected to be completed until 2028. Furthermore, the third fab of the trio, also slated for advanced 2nm chip production, isn’t projected to be finished until the end of the decade. This makes JW Kuo’s bold statement to the Taipei Times literally pointless to affirm.
That’s not the end of it though, as TSMC plans to pair GAA with backside power delivery, which is a fancy way of saying the power lines will be routed below the transistor, not above. It’s a clever and intricate design that frees up space for the signals on top, but implementing it is no small feat. So, what’s the reality of it all? Well, combining these two innovations should make things more complex for TSMC’s engineers and fabs. For reference, TSMC actually decided not to include BSPD in its N2P node on 2nm, but it is set to make an appearance through its A16 node, also referred to as 1.6nm.
Will TSMC’s 2nm roadmap hold steady?
TSMC’s 2025 target for 2nm mass production sounds bold, because it is. Even without taking any of the above into consideration, this is the same company that repeatedly pushed back the launch of its 3nm process before finally entering high-volume production last year. And 3nm wasn’t even as big of a leap as 2nm with all of its added complexities of GAA and backside power delivery promises to be.
Intel and Samsung are hardly setting better examples, as Intel’s 18A process (equivalent to 2nm) has hit delay after delay, and Samsung is still ironing out issues with its own GAA-based nodes. It’s worth noting that it seems that none of the big players in the semiconductor industry are coasting to the finish line regarding 2nm.
TSMC’s claims about 2nm are what we typically put down as some classic industry chest-thumping. The chipmaker will eventually deliver on its roadmap, but whether it can do so by 2025 is another matter entirely. Hitting that timeline would mean overcoming some challenges in design, manufacturing, and supply chain management. Hey, it’s possible that TSMC might pull it off. After all, it often does, which is one reason they remain the leader in processor manufacturing.
At the same time, there is information that Intel and Samsung are already working on a response to TSMC. So, Samsung plans to hold the Foundry and SAFE Forum conference on June 12-13, where it can present an updated roadmap and announce the postponement of the start of mass production of 1nm chips from 2027 to 2026.
